Conventionally, the hardware design of a processor and its associated instruction set is done separately from the writing of application programs for the processor. The processor may be designed using a hardware description language (HDL) such as VHDL or Verilog. The processor HDL description is used to create a processor in an application specific integrated circuit (ASIC) such as the Pentium® processor of Intel® Corp. of Santa Clara, Calif. or in a Field Programmable Gate Array (FPGA), such as the MicroBlaze™ processor of Xilinx Inc. of San Jose, Calif. The application programs are written after the processor has been implemented as an ASIC or in a FPGA. The application programs are typically written in a higher level computer language such as C, C++, VB/VBA, Java, or assembly language, which must be compiled and/or assembled into object code in order to be executed by the processor.
FIG. 1 is a prior art flowchart for implementing a processor in an FPGA (or CPLD) and executing an application program on the processor. There are conventionally two sub-flows, a hardware flow 100 and a software flow 104. For the hardware flow 100, at step 110, a HDL description is obtained by developing a new description or by using or modifying an existing description. Associated with the HDL description of the processor is the processor's instruction set, which includes the op-codes. At step 112 the HDL description is synthesized into a netlist, using a synthesis tool such as the FPGA Compiler II from Synopsys® Inc. of Mountain View Calif. The synthesis tool typically uses conventional minimization techniques to reduce the number of logic gates (and other resources) needed to implement the processor. In the case of an FPGA (or CPLD), a place and route tool is next used to determine how the programmable logic blocks in the FPGA (or CPLD) should be placed and routed in the FPGA (or CPLD) (step 112). At step 114 the FPGA (or CPLD) is actually configured using the placed and routed netlist.
The software flow 104 starts at step 120 with writing a source code program using the instruction set for the processor in the hardware flow 100. At step 122 the source code is complied into object code, i.e., binary code. The object code is stored in a memory, such as a programmable read-only memory (PROM) connected to the processor (step 124). At step 126 the object code is executed by the processor configured in the FPGA.
The flowchart of FIG. 1 has in the past been used for the traditional general purpose processor with its “one size fits all” instruction set. However, in recent times a major problem developed—the general purpose processor could not meet the performance criteria for certain application specific domains such as digital signal processing (DSP). Thus processors and their instruction sets were customized for specific application domains. An example, is the DSP processor of Texas Instruments of Dallas, Tex. Another example is the graphics processor of nVIDIA Corporation of Santa Clara, Calif.
While the processors and their instruction sets became more application oriented, the design flow of hardware and software of FIG. 1 was still used. However, the greater correlation between the application domain as represented by the application program, and the customized instruction set and processor, indicated that there was a need for improving the integration of the hardware and software flows of FIG. 1.
Therefore, as the need for application specific processors continues, there is also a need for improved techniques for developing these application specific processors.